The present invention relates to an address space control apparatus for virtual memory systems and, more particularly, to an address space control apparatus for controlling multiple virtual address spaces suitable for handling very large quantities of data.
U.S. Pat. No. 4,355,355 entitled "Address Generating Mechanism for Multiple Virtual Spaces" by J. R. Butwell et al. discloses a multiple virtual memory system which enables a program to have access to multiple virtual address spaces. In that system, each general-purpose register (GR) is associated with an access register (AR) containing a segment table origin (STO). Each STO locates a segment table for address translation, thereby defining one address space. When a GR is designated as a base register (BR) by an instruction, the contents of the AR associated with that GR are read out to provide an STO. A special, non-priviliged instruction is also provided to change the contents of each AR. This instruction loads a designated AR with data in a main storage area defined by the contents of a control register.
Thus, by changing the contents of an AR or by designating a different GR as a BR, a program can make use of multiple STO's, hence of multiple address spaces.
This system has provided a definite improvement to virtual memory systems in that a program can gain access to multiple address spaces. For example, a collection of data too bulky to be accommodated by a single address space can be easily handled by this system.
However, the above-described system is not without its share of room for further improvement. Where address spaces are to be switched, the system requires changing the contents of an AR, or designating a different BR, as described above. To change the AR contents requires gaining access to main memory. In turn, gaining access to main memory involves translation from logical to real addresses. It takes time to carry out these operations. In particular, when it is necessary to switch address spaces frequently, there occurs a marked drop in processing speed.
Meanwhile, designating different BR's poses no such challenges. Instead, however, each instruction is required to designate an appropriate GR as a BR. This requirement may present extra burdens when the result of a preceding operation determines the address space to be accessed, or when address spaces are to be switched halfway through repeated processing. For example, there may arise a need to switch address spaces while a subroutine is being executed repeatedly on successive portions of data in large quantities. In such a case, each BR-designating field must be rewritten in all or numerous selected instructions within the subroutine. In addition, the number of address spaces that are accessible under this method can not exceed the number of GR's that may be used as BR's. To use further address spaces requires changing the contents of AR's as described above.